Timing of the s88-Bus

Current situation

Until now there no official specification for the s88 bus. In the following I try to define a reasonable value by looking at common used chips and wiring.

The original s88 feedback module comes with HEF4014 chips. These IC's have (at 5V) a tsetup up to 35ns and a thold up to 30ns. The propagation delay tpd amounts to 260ns.
The wiring introduces both propagation delay and capacitive loading. Typical cables have a tpd of 6,6ns/m, (resulting in approx. 200ns for 30ms maximum length). The capacitive load acts together with the output resistance as low pass filter. I.E. 44pF/m and a source resistance of 250 Ohms will give a trc of 11ns/m.

The timing of all known command stations (IB, HSI88, MC, 6050, etc.) is generated with slow bit banging, changing states after some 10µs. Some s88 module make use of this slow timing and implement the interface in software with a micro controller.

Clockrates existing Interfaces
Command Station t(high_min) t(low_min) Comment
Tams 100µs 100µs low jitter, scan every 4.9ms
Littfinski HSI88 150µs 150µs low jitter
Intellibox 30µs 25µs high jitter, average approx. 70µs
Nano-X-s88 50µs 50µs Jitter only in t-low
OpenDCC 20µs 20µs Jitter, adjustable timing (via CV)
ECoS 25µs 25µs unofficial value.
ESU rejected to provide data and claimed 'IP right issues'.

It looks like some implementations (the S88 bus is often implemented via a microcontroller) rely on this relaxed timing values. Depending on the vendor the appropriate routines vary in their speed. (Blücher seems to require at least 140µs cycle time, railway-lauf.de at least 200µs).

Sources for trouble:

Timing definitions

S88 Timing